1. Field of the Invention
This invention relates to a cell structure for plasma display panels.
The present application claims priority from Japanese Application No. 2002-291816, the disclosure of which is incorporated herein by reference.
2. Description of the Related Art
In recent years, plasma display panels (hereinafter referred to as “PDP”) have been spotlighted as a large-sized flat color-screen display and the widespread proliferation thereof in ordinary homes and the like has been planned.
FIG. 1 to FIG. 3 illustrate the cell structure of a conventional PDP.
FIG. 1 is a schematic plan view illustrating the cell structure of the conventional PDP. FIG. 2 is a sectional view taken along the VA—VA line in FIG. 1. FIG. 3 is a sectional view taken along the VB—VB line.
The conventional PDP has a front glass substrate 1 serving as the display screen and having a back surface on which a plurality of row electrode pairs (X, Y) each forming a display line L are arranged in parallel and extend in the row direction (the right-left direction in FIG. 1) of the front glass substrate 1.
Each of the row electrodes X and Y is constituted of transparent electrodes Xa (Ya) each formed of a T-shaped transparent conductive film made of ITO or the like, and a metal-film-made bus electrode Xb (Yb) extending in the row direction of the front glass substrate 1 and connected to the narrow proximal ends (i.e. the foot of the T shape) of the transparent electrodes Xa (Ya).
The row electrodes X and Y are regularly arranged in alternate positions in the column direction (the vertical direction in FIG. 1) of the front glass substrate 1. Then the transparent electrodes Xa and Ya, which are regularly lined up along the corresponding bus electrodes Xb and Yb to be opposite to each other, extend toward each other so that the widen top edges of the opposing transparent electrodes Xa and Ya face each other with a discharge gap g set at a required distance in between.
Each of the bus electrodes Xb, Yb is formed in a double layer construction consisting of a black conductive layer Xb1 (Yb1) positioned close to the display screen and a main conductive layer Xb2 (Yb2) positioned behind this.
On the back surface of the front glass substrate 1, a black-or dark-colored light absorption layer BS extends in parallel in the row direction between the back-to-back positioned bus electrodes Xb, Yb of the respective row electrode pairs (X, Y) adjacent to each other in the column direction.
In addition, on the back surface of the front glass substrate 1, a dielectric layer 2 is formed so as to cover the row electrode pairs (X, Y). On the back surface of the dielectric layer 2, additional dielectric layers 2A protrude backward from the dielectric layer 2, and each extend in parallel to the bus electrodes Xb, Yb in a position opposite the adjacent bus electrodes Xb and Yb of the respective row electrode pairs (X, Y) positioned alongside each other, and opposite the area between the adjacent bus electrode Xb and bus electrode Yb.
An MgO protective layer 3 is formed on the back surfaces of the dielectric layers 2 and the additional dielectric layers 2A.
In turn, a back glass substrate 4 placed in parallel to the front glass substrate 1 has a surface, facing toward the display screen, on which column electrodes D are arranged in parallel to each other at predetermined intervals and each extends opposite the paired transparent electrodes Xa and Ya of each row electrode pair (X, Y) in a direction at right angles to the row electrode pairs (X, Y) (i.e. the column direction).
On the surface of the back glass substrate 4 facing toward the display screen, a white-colored column-electrode protective layer (dielectric layer) 5 is further formed and covers the column electrodes D, and white-colored partition walls 6 are formed on the column-electrode protective layer 5.
Each of the partition walls 6 is shaped in a ladder pattern formed of a pair of transverse walls 6A extending in the row direction in positions respectively opposite to the bus electrodes Xb and Yb in each row electrode pair (X, Y), and a plurality of vertical walls 6B each extending in the column direction between the paired transverse walls 6A and at a midpoint between the adjacent column electrodes D.
The ladder-patterned partition walls 6 are arranged in parallel to each other in such a manner as to form an interstice SL opposite the light absorption layer BS and between the adjacent transverse walls 6A of the respective partition walls 6 positioned alongside each other in the column direction.
The ladder-patterned partition walls 6 partition a discharge space S defined between the front glass substrate 1 and the back glass substrate 2 into areas each opposite to the paired transparent electrodes Xa and Ya in each row electrode pair (X, Y) to form quadrangular discharge cells C.
Inside each of the discharge cells C, a phosphor layer 7 covers five faces, namely, the face of the column-electrode protective layer 5 and the four side faces of the transverse walls 6A and the vertical walls 6B of the partition wall 6. One of the three colors, red, green and blue, is applied in turn to the individual phosphor layer 7 so that the red, green and blue colors in the individual discharge cells C are arranged in order in the row direction.
The discharge space S is filled with a discharge gas.
To display an image in the conventional PDP, addressing takes place initially in order to selectively cause a discharge between one row electrode in the row electrode pair (X, Y) and the column electrode D in each discharge cell C for distribution of the lighted cells (discharge cells C having wall charges generated on the dielectric layer 2) and the non-lighted cells (discharge cells C having no wall charges generated on the dielectric layer 2) in all the display lines L over the panel surface in accordance with the image to be displayed.
After completion of the addressing, simultaneously in all the display lines L, a discharge-sustaining pulse is applied alternately to the row electrodes X and Y of each row electrode pair (X, Y) to trigger a surface discharge in each lighted cell with every application of the discharge-sustaining pulse. This surface discharge generates ultraviolet light which then excites each of the red-, green-, and blue-colored phosphor layers 7 formed in the individual lighted cells C to emit visible light for the generation of the image to be displayed.
The conventional PDP structured as described above has black-colored conductive layers Xb1, Yb1 formed on the respective bus electrodes Xb, Yb, and the black- or dark-colored light absorption layer BS formed between the bus electrodes Xb and Yb backing on each other in between the display lines L, in order to prevent reflection of ambient light incident to the panel's non-light emission area formed between the display lines L for achievement of improvement in image contrast on the panel surface.
Further, the above conventional PDP has a white color applied to the column-electrode protective layer 5 and the partition wall 6 which are formed on the back glass substrate 4 to cause the light emitted from the phosphor layer 7 and then travelling toward the back glass substrate 4 to reflect toward the front glass substrate 1, in order to enhance the use efficiency of the light for improvement in brightness of the image displayed on the panel screen.
However, in the conventional PDPs having such cell structure, ambient light entering at an angle from the light emission area (the area in which the discharge cells C is formed) of the panel screen may not be blocked by the black conductive layers Xb1, Yb1 of the row electrodes X, Y and the light absorption layer BS, and then may reach inside the interstice SL in the non-light emission area, and may possibly be reflected by the white column-electrode protective layer 5 and partition wall 6 which face the interstice SL. Thus, the reflection of the ambient light coming from the non-light emission area makes it impossible to prevent a decrease in contrast of an image displayed on the panel screen.